Computer-aided design methodology for linearity enhancement of multiwatt GaN HEMT amplifiers using multiple parallel devices

This article presents a design methodology for linearizing GaN HEMT amplifiers based on splitting a large FET into multiple parallel FETs with same total gate periph- ery and by biasing them individually. By varying the biases, the magnitude and the phase of the IMD3 components at the output of FET changes. A detailed simulation methodology using commercial microwave CAD software is presented. Simulation results show that by biasing one device in Class AB and other(s) in deep Class AB mode, IMD3 components of parallel FETs can be made out of phase to each other leading to cancellation and improvement in linearity. Three prototype circuits were simulated using (a) a single 5 mm FET (1 × 5 mm), (b) two parallel 2.5 mm FETs (2 × 2.5 mm), and (c) four parallel 1.25 mm FETs (4 × 1.25 mm), for a total gate periphery of 5 mm, over the frequency range of 0.8 to 1.0 GHz. IMD3 improvement up to 20 dBc was achieved with the 4 × 1.25 mm circuit when the FET biases were optimized. Measurement results show improvement in linearity up to 20 dBc for 4 × 1.25 mm circuit. The proposed method improves linearity without a substantial penalty on the power consumption and is straightforward to implement.

Published_Computer-aided design methodology.pdf